Huawei’s recently disclosed patent for a quad-chiplet packaging design, rumored to underpin its next-generation Ascend 910D AI accelerator, has attracted widespread attention. This sophisticated packaging strategy closely mirrors NVIDIA’s forthcoming Rubin Ultra and signals a significant step toward closing the performance gap while navigating around U.S. technology restrictions.
What’s in the Patent?
Filed in April 2024 under PCT/CN2024/086375 and now under substantive review by China’s IP office, the patent outlines a four-chip integration achieved via advanced Chip-on-Wafer-on-Substrate–Local (CoWoS L) style packaging. Rather than using a simple interposer, it proposes bridge-like vertical interconnects within a silicon substrate, enabling ultra-high-speed data exchange between four compute dies. Key innovations include:
· Optimized interposer routing that rearranges logic blocks and dynamic interface reconfiguration to eliminate signal conflicts.
· Integrated re-distribution layers (RDL) and active components like embedded registers to boost long distance signal integrity.
· Embedded multi-layer substrate design to reduce package thickness and improve routing density.
· High-density inter-die exchanges, ideal for compute and optical communication units.
· Reliance on mature foundry nodes like SMIC 14 nm and domestic packaging lines to balance cost and yield.
These features aim to efficiently integrate multiple dies and high-bandwidth memory (HBM) within a single package—very much in line with CoWoS L innovations.
Strategic Alignment with NVIDIA Rubin Ultra
NVIDIA’s Rubin Ultra, slated for 2027, builds on the Rubin 2026 platform by packing four GPU dies with multiple HBM4 stacks through CoWoS L technology. Huawei’s patent echoes the same bridge-style die integration seen in NVIDIA’s roadmap. Tom’s Hardware, HyperAI, TrendForce, GameGPU, and Huawei Central all highlight the striking architectural parallels.
Enormous Die & Memory Scale
One of the more staggering estimates: each Ascend 910B compute die measures ~665 mm². A quad chiplet design would bring compute dies to ~2,660 mm². Adding 16 HBM chiplets at ~85 mm² each expands the memory footprint to ~1,366 mm²—totaling an approximate 4,020 mm² package area. By TSMC standards, that’s equivalent to five EUV reticle sizes, aligning with large-scale packaging concepts projected for 2026 CoWoS L.
Why This Matters
Sanctions work-around
Huawei and SMIC may not have access to leading-edge EUV tools, but they can harness packaging to interlink older nodes and achieve high-end performance—fully domestically managed.
Cost savings
By leveraging mature 14 nm processes and local suppliers, Huawei could reduce total system costs of Ascend 910D by around 40% compared to NVIDIA’s H200—closing the cost performance gap significantly.
Improved compute density
Officials estimate that a quad chiplet card could deliver ~1,400 TFLOPS in FP16, closing in on NVIDIA H100 levels. Support for existing CUDA X stack further reduces adoption friction for enterprise clients.
Strategic R&D push
Huawei’s joint “3D Integration Lab” with Tsinghua University focuses on advanced 3D bonding and glass interposers. Meanwhile, Chinese substrate suppliers aim to build monthly capacities of 100,000 panels by 2026 to meet high-density target markets.
Technical & Commercial Hurdles
· Software compatibility
Huawei’s CANN software currently supports only a limited subset of mainstream AI frameworks, lacking CUDA interoperability.
· Packaging footprint vs. yield
Enormous package dimensions (~4,000 mm²) pose manufacturing challenges. Current yields hover around 65%, demanding improvements to ~85% for mass production.
· Thermal management issues
Integrating four compute dies and 16 HBM stacks presents serious heat dissipation burdens.
· Time to market lags
Sample testing reportedly began in May, but full certification and market readiness may trail NVIDIA by months.
The Road Ahead
If Huawei surmounts these challenges, Ascend 910D could mark a significant systemic shift—delivering high-density AI accelerators built on accessible processes and boosting China’s self-reliance in semiconductor innovation. Meanwhile, NVIDIA marches ahead—with Rubin (2026) and Rubin Ultra (2027) launching cutting-edge GPU and CPU stacks integrated via CoWoS L for HBM rich performance.
The outcome will influence international markets shaping AI infrastructure investment, supply-chain positioning, and geopolitical tech landscapes. Success for both players may usher in a new era of package-centric “chips-first” competition—highlighting that today’s AI arms race isn’t just about process technology, but integration and systems.
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