As a representative silicon bridge-based 2.5D packaging technology, EMIB (Embedded Multi-die Interconnect Bridge) has recently been updated to EMIB-T, designed to support HBM4/4e memory standards. This article takes a closer look at this evolving technology.
At the Electronic Components Technology Conference (ECTC) held a couple of months ago, Intel unveiled several breakthroughs in chip packaging, including EMIB-T. This iteration supports larger package dimensions and enhanced power delivery capabilities necessary for memory technologies like HBM4/4e. Intel had previously shared details about EMIB-T at earlier events this year, including IEDM and the Intel Foundry Direct Connect (IFDC).
When Intel Foundry announced the full opening of its OSAT (Outsourced Semiconductor Assembly and Test) model earlier this year, EMIB was highlighted as a key offering for customers. This technology, distinct from the more commonly discussed interposer-based 2.5D packaging, is poised to play an increasingly vital role in the "More than Moore" era. This article explores EMIB and its upgraded EMIB-T variant, providing a technical foundation for enthusiasts of advanced packaging.
Silicon Bridge-Based 2.5D Advanced Packaging
2.5D/3D advanced packaging is a frequently cited solution in the post-Moore era. Its value proposition in extending scaling is well-understood, and such packaging is now common in consumer chips, exemplified by Intel Core Ultra processors and Apple Mx Ultra chips.
The rationale for 2.5D/3D packaging is clear: when monolithic dies can no longer accommodate more transistors due to reticle limits of lithography equipment, integrating multiple dies through advanced packaging becomes essential. Furthermore, individual dies can be manufactured using different process nodes optimized for their function – improving overall cost efficiency, especially when not all components require the most advanced processes. These advantages are central to the value of 2.5D/3D packaging and chiplet architectures, enabling continued gains in transistor count, compute power, and efficiency beyond Moore's Law.
Compared to traditional Multi-Chip Packages (MCPs) where subsystems (CPU, GPU, accelerator, memory) are placed separately on a board, MCPs inherently save board space. 2.5D/3D advanced packaging further increases MCP integration, shrinking package size while boosting interconnect density and bandwidth, reducing signal integrity loss and power consumption.
Foundries and OSATs implement advanced packaging differently. Well-known examples include TSMC's CoWoS, particularly CoWoS-S, which uses a silicon interposer for die-to-die connections. Other CoWoS variants employ RDLs (Redistribution Layers) or interposers incorporating LSI (Local Silicon Interconnect). Intel's EMIB represents a different 2.5D approach. EMIB utilizes small silicon bridges embedded within the organic substrate to connect adjacent dies – the dies interconnect over a "slotted" bridge area on the substrate.
As 2.5D packaging gains traction, Intel has recently emphasized EMIB's cost advantage. Large interposers or RDL interposers covering the entire package area are expensive. In contrast, EMIB bridges are tiny silicon slivers. Intel Foundry stated that a single wafer can yield thousands of these bridges, achieving extremely high wafer utilization.
Intel's data contrasts EMIB bridge utilization (~90% of a wafer) with that of large Si/RDL interposers needed for today's large AI chips (exceeding 8x the reticle limit when including HBM dies), which only achieve ~60% utilization. This gives EMIB a significant cost edge, not even factoring in manufacturing yield differences.
Silicon bridge solutions do face challenges, including potentially lower interconnect density compared to some alternatives, reduced routing flexibility, and complexities in managing thermal and signal integrity for the overall package design.
Nevertheless, EMIB stands as a highly promising, relatively low-cost 2.5D MCP solution for connecting diverse components like CPUs, GPUs, FPGAs, I/O blocks, and memory dies. Its potential is amplified by the prospect of emerging technologies like glass cores potentially finding earlier adoption within bridge-based packaging schemes.
Examining EMIB-Packaged Chips
EMIB isn't the only "bridge" technology. Apple's M2 Ultra, for instance, uses TSMC's InFO-LSI silicon bridge solution. A 2023 paper in the Journal of Microelectronics and Electronic Packaging ("State-of-the-Art in Chiplets Horizontal Communications") also mentions IBM's DBHi, fan-out EMC (Epoxy Mold Compound) bridges (e.g., SPIL's FO-EB, ASE's sFOCoS), and flexible bridges. This article focuses on EMIB due to its established production history and prominence.
Based on public information, Intel's first commercial use of EMIB dates back to the 2018 Core 8th Gen (Kaby Lake-G) processor. This unique processor incorporated an AMD GPU die alongside 4GB of HBM2 memory. The connection between the GPU die and the HBM stacks utilized EMIB silicon bridges. SEM cross-sections reveal the bridge structure embedded within the package substrate.
Key characteristics of EMIB implementation include:
1. Chiplets require two bump types (C4 for die-to-package connections, C2 for connections to the EMIB bridge). The bridge itself is bumpless.
2. The bridge is embedded within the substrate, covered by a laminated dielectric layer.
3. Chiplets are bonded onto both the substrate and the bridge.
The EMIB manufacturing flow involves two main parts: fabricating the EMIB bridges and creating the substrate with embedded bridges.
· Bridge Fabrication: Build RDL layers (requiring fine line width/spacing) on a silicon wafer. Attach the non-RDL side to a Die-Attach Film (DAF). Dice the wafer into individual EMIB bridges.
· Substrate Fabrication: Place the diced EMIB bridges (with DAF) into pre-formed cavities on the substrate's copper foil layer. Laminate a dielectric film over the entire substrate. Drill vias through this film and electroplate them with copper to establish electrical connections to the bridge's contact pads and provide lateral substrate routing. A subsequent dielectric layer is laminated, drilled, and plated to form vias for the C2 (finer pitch) and C4 bumps. This prepares the substrate for chiplet bonding.
Research identifies key challenges: creating organic substrates with precise cavities for the bridges, laminating subsequent layers with the required temperature/pressure profiles to ensure surface planarity for bonding, and the bonding process itself. Intel has cited challenges including bonding techniques, manufacturing throughput, die warpage, surface quality, DAF material design, die transfer, via-to-die-pad alignment, and integration considerations.
However, Intel clarified in a 2021 SemiWiki interview that EMIB builds upon standard packaging flows, adding steps for cavity formation, bridge placement (using adhesive), and the final dielectric/metal lamination with vias. A crucial design/manufacturing consideration is the dual-bump requirement on chiplets. Intel emphasized significant engineering effort to define the C4 and C2 bumps, focusing on bump height control, solder volume, collaboration with suppliers, and developing a void-free epoxy underfill process. By 2021, these materials, bumps, and bonding processes were qualified for High-Volume Manufacturing (HVM).
Key Parameters
Beyond the known 55μm bump pitch for the initial EMIB generation, research papers provide other key specs:
· Minimum metal L/S/H (Line width/Spacing/Thickness): 2/2/2μm
· Silicon bridge size: Typically 2x2mm to 8x8mm, mostly <5x5mm
· Dielectric layer thickness: ~2μm
· RDL layers: ≤4
Intel's 2021 data largely corroborates this. They emphasized that EMIB interconnect design involves complex trade-offs between density, power, and bandwidth. Achieving targets requires optimizing driver size, receiver sensitivity (often unterminated/capacitive loading for lower power), line width/spacing, bump pitch, channel length, metal thickness, inter-layer dielectric, and signal shielding schemes (e.g., S1G1, S2G1, S3G1).
It's important to note that the cited data points are from 2021-2023 sources. The newer EMIB generation has already reduced bump pitch to 45μm, with Intel stating ongoing efforts towards higher edge density, tighter pitches, and finer lines.
Regarding routing flexibility, Intel has noted that EMIB supports various bridge placement options, including connections between asymmetric dies and accommodating irregular chip layouts, offering more flexibility than intuition might suggest, though likely still less than full-interposer solutions. SemiWiki's 2021 article also provided EMIB electrical characteristic data.
The Evolution to EMIB-T
The recently announced EMIB-T represents an evolution of EMIB, characterized by the addition of TSVs (Through-Silicon Vias – hence the "T") and support for finer bump pitches. While detailed technical specifications remain limited, the core enhancements are known.
Tom's Hardware reported that EMIB-T improves power delivery efficiency and boosts die-to-die communication speeds. Standard EMIB connections reportedly suffered voltage drop issues due to "cantilevered" power delivery paths (longer, more resistive routes around the bridge). EMIB-T addresses this by integrating TSVs within the bridge die, enabling direct, low-resistance power delivery from the package bottom. This is crucial for integrating power-hungry components like HBM4/4e memory.
Reports indicate these TSVs also facilitate high-speed signal transmission, increasing die-to-die bandwidth. This enables HBM4/4e integration and supports UCIe-A interconnects, pushing data rates to 32Gb/s or higher. To mitigate noise from combined power/signal routing, Intel integrated high-performance MIM (Metal-Insulator-Metal) capacitors within the silicon bridge for enhanced electrical stability.
EMIB-T also supports significantly larger package sizes (120x180mm), accommodating over 38 bridges and 12 reticle-sized dies per package. Key process updates include reducing bump pitch from 55μm to 45μm, with Intel suggesting EMIB-T could soon reach 35μm and is developing 25μm capability.
Some reports mention power efficiency figures: standard EMIB achieving a minimum of ~0.3 pJ/bit, and EMIB-T potentially reaching ~0.25 pJ/bit. However, these values are highly dependent on chiplet type, process, and memory standards.
EDN reported close collaboration between Intel Foundry and major EDA vendors on developing design, analysis, and verification flows for EMIB-T packaging. This aligns with Intel Foundry's OSAT strategy, building on its announcement last year of industry-standard tool support for EMIB. (Note: Details on combining EMIB with Intel's Foveros 3D packaging for "3.5D" or Co-EMIB are beyond this article's scope).
Intel Foundry's experience packaging dies from multiple sources dates back to the 2018 Kaby Lake-G (featuring dies from TSMC, GlobalFoundries, and Intel). This history positions them well to offer advanced packaging services for fabless clients using diverse front-end manufacturing sources.
Why Intel Foundry is Pushing EMIB
EMIB is a strategic focus for Intel Foundry for several reasons:
1. AI/HPC Demand: The surge in AI and high-performance computing creates significant market demand for packaging technologies like EMIB. EMIB-T's support for faster memory (HBM4/4e), more dies, and larger packages directly targets AI/HPC chip requirements.
2. Capacity Claim: Intel Foundry has publicly asserted it possesses over 2x the available 2.5D advanced packaging capacity of its main competitor (implicitly TSMC), positioning it to meet the rapidly expanding AI chip market demand. Consequently, EMIB is expected to be a major revenue driver for Intel Foundry's packaging services.
Key Terminology Clarification:
· EMIB: Embedded Multi-die Interconnect Bridge
· OSAT: Outsourced Semiconductor Assembly and Test
· HBM: High Bandwidth Memory
· TSV: Through-Silicon Via
· RDL: Redistribution Layer
· Interposer: A silicon or organic layer facilitating high-density connections between dies in 2.5D packaging.
· MCP: Multi-Chip Package
· Chiplet: A small, functional die designed to be integrated with others in an advanced package.
· Bump (C4, C2): Solder balls/connections on a die (C4 typically larger for substrate connection, C2 smaller/finer pitch for bridge connection).
· DAF: Die-Attach Film
· HVM: High-Volume Manufacturing
· L/S/H: Line Width / Spacing / Thickness (in interconnect metallization).
· MIM Capacitor: Metal-Insulator-Metal Capacitor (integrated for decoupling).
· UCIe: Universal Chiplet Interconnect Express (an open industry standard).
· pJ/bit: Picojoules per bit (a measure of energy efficiency for data transmission).
